This application contains subject matter similar to subject matter disclosed in copending U.S. patent applications: Ser. No. 09/679,372, filed on Oct. 5, 2000, now U.S. Pat. No. 6,465,349 which issued Oct. 15, 2002; Ser. No. 09/679,374, filed on Oct. 5, 2000, now U.S. Pat. No. 6,383,880 which issued May 7, 2002; Ser. No. 09/679,880, filed on Oct. 5, 2000, now U.S. Pat. No. 6,521,529 which issued Feb. 18, 2003; Ser. No. 09/679,375, filed on Oct. 5, 2000, now U.S. Pat. No. 6,545,370 which issued Apr. 8, 2003; and Ser. No. 09/679,871, filed Oct. 5, 2000, now U.S. Pat. No. 6,548,403 which issued Apr. 15, 2003.
The present invention relates to the fabrication of semiconductor devices, particularly to self-aligned silicide (salicide) technology, and the resulting semiconductor devices. The present invention is particularly applicable to ultra large scale integrated circuit (ULSI) systems having features in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate exhibiting the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the RxC product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Various metal silicides have been employed in salicide technology, such as titanium, tungsten, and cobalt. Nickel, however, offers particularly advantages vis-xc3xa1-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide and can be formed in a single heating step at a relatively low temperature of about 250xc2x0 C. to about 600xc2x0 C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra-shallow source/drain junctions.
In conventional salicide technology, a layer of the metal is deposited on the gate electrode and on the exposed surfaces of the source/drain regions, followed by heating to react the metal with underlying silicon to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts on the upper surface of the gate electrode and on the source/drain regions. In implementing salicide technology, it was also found advantageous to employ silicon nitride sidewall spacers, since silicon nitride is highly conformal and enhances device performance, particularly for p-type transistors. However, although silicon nitride spacers are advantageous from such processing standpoints, it was found extremely difficult to effect nickel silicidation of the gate electrode and source/drain regions without undesirable nickel silicide bridging and, hence, short circuiting, therebetween along the surface of the silicon nitride sidewall spacers.
Accordingly, there exists a need for salicide methodology enabling the implementation of nickel silicide interconnection systems without bridging between the nickel silicide layers on the gate electrode and the source/drain regions, particularly when employing silicon nitride sidewall spacers on the gate electrode.
An advantage of the present invention is a method of manufacturing a semiconductor device having nickel silicide contacts on a gate electrode and associated source/drain regions without bridging therebetween along insulative sidewall spacers, notably silicon nitride sidewall spacers.
Another advantage of the present invention is a semiconductor device having nickel silicide contacts on a gate electrode and on associated source/drain regions without bridging therebetween along insulative sidewall spacers, particularly silicon nitride sidewall spacers.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon gate electrode, having opposing side surfaces, on a substrate with a gate insulating layer therebetween; forming silicon nitride sidewall spacers on the opposing side surfaces of the gate electrode leaving exposed adjacent surfaces of the substrate; treating the silicon nitride sidewall spacers with a nitrogen oxide plasma; depositing a layer of nickel on the gate electrode and on the exposed substrate surfaces; and heating to react the layer of nickel with underlying silicon to form a layer of nickel silicide on the gate electrode and layers of nickel silicide on the exposed surfaces of the substrate.
Embodiments of the present invention include forming the silicon nitride sidewall spacers with a refractive index of about 1.95 to about 2.02, and treating the silicon nitride spacers in a nitrogen oxide plasma to form a nitrogen-rich/silicon-starved surface region deficient in unbonded silicon, i.e., deficient in silicon having dangling bonds, at a thickness of about 100 xc3x85 to about 400 xc3x85 and having a refractive index less than about 1.95. Embodiments of the present invention further include forming an oxide liner on the opposing side surfaces of the gate electrode prior to forming the silicon nitride sidewall spacers, sputter etching in argon before depositing the layer of nickel to remove contamination and forming the nickel silicide layers at a temperature of about 400xc2x0 C. to about 600xc2x0 C.
Another aspect of the present invention is a semiconductor device comprising: a gate electrode, having opposing side surfaces and an upper surface, on a semiconductor substrate with a gate insulating layer therebetween; silicon nitride sidewall spacers on the opposing side surfaces of the gate electrode; a layer of nickel silicide on the upper surface of the gate electrode; and a layer of nickel silicide on the substrate surface adjacent each silicon nitride sidewall spacer, wherein each silicon nitride sidewall spacer comprises a surface region having a refractive index less than the remainder of the silicon nitride sidewall spacer. Embodiments of the present invention include silicon nitride sidewall spacers with a surface region having a refractive index of about 1.95 while the remainder of the silicon nitride sidewall spacer has a refractive index of about 1.98 to about 2.02, wherein, the surface region contains more nitrogen and less silicon with dangling bonds than the remainder of the silicon nitride sidewall spacer and contains silicon oxide.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.